Brief introduction by the organizers on the motivation for as well as the format and the contents of the DATA-DREAM workshop in DATE 2022.

Taking decisions in the context of the data economy requires a deep understanding of the market and its projections. Investment in technologies should consider the value of indicators associated to the potential growth of the market, competitors, size of the ecosystem or a view on the skills gap. This presentation will offer updated figures elaborated by the Data Market Study run by IDC for 2021-2023 and will position the figures in a set of potential scenarios that will define the performance of the EU in a data-driven economy. Attendees will learn about the value of indicators such as data professionals and the skills gap, data companies, data suppliers, data economy, the value of the data market or the international dimension bringing some knowledge on markets outside the EU (US, Brazil, Japan, China).
The presentation will also look at major developments and initiatives in Europe of relevance to the development of the data economy and will reflect on the relationship between the different technologies that are needed to maximize competitiveness and keep digital sovereignty.

At RIKEN Center for Computational Science (R-CCS), we have been developing an experimental FPGA Cluster named "ESSPER (Elastic and Scalable System for high-PErformance Reconfigurable computing)," which is a research platform for reconfigurable HPC. ESSPER is composed of sixteen Intel Stratix 10 SX FPGAs which are connected to each other by a dedicated 100Gbps inter-FPGA network. We have developed our own Shell (SoC) and its software APIs for the FPGAs supporting inter-FPGA communication. The FPGA host servers are connected to a 100Gbps Infiniband switch, which allows distant servers to remotely access the FPGAs by using a software bridged Intel's OPAE FPGA driver, called R-OPAE. By 100Gbps Infiniband network and R-OPAE, ESSPER is actually connected to the world's fastest supercomputer, Fugaku, deployed in RIKEN, so that using Fugaku we can program bitstreams onto FPGAs remotely using R-OPAE, and off-load tasks to the FPGAs. In this talk, I introduce our ESSPER's concept, system stack of hardware and software, programming environment, under-development applications as well as our future prospects for reconfigurable HPC.

Information technology has entered the age of heterogeneous computing. Across a variety of application domains, computer systems rely on highly heterogeneous architectures that combine multiple general-purpose processors with many specialized hardware accelerators. The complexity of these systems, however, threatens to widen the gap between the capabilities provided by semiconductor technologies and the productivity of computer engineers. Open-source hardware is a promising avenue to address this challenge by enabling design reuse and collaboration. ESP is an open-source research platform for system-on-chip design that combines a scalable tile-based architecture and a flexible system-level design methodology. Conceived as a heterogeneous system integration platform, ESP is intrinsically suited to foster collaborative engineering across the open-source hardware community.

Sparse linear algebra operations are widely used in numerous application domains such as graph processing, machine learning, and scientific computing. These operations are typically more challenging to accelerate due to low operational intensity and irregular data access patterns.

This talk presents our recent investigation into near-memory hardware acceleration for sparse processing. Specifically, I will discuss the importance of co-designing the sparse storage format and  accelerator architecture to maximize the bandwidth utilization and compute occupancy. As a case study, I will introduce GraphLily, a graph linear algebra overlay for accelerating graph processing on HBM-equipped FPGAs. GraphLily supports a rich set of graph algorithms by adopting the GraphBLAS programming interface, which formulates graph algorithms as sparse linear algebra operations.