DATE 2022 Technical Programme Committee

Track D: Design Methods and Tools

addresses design automation, design tools and hardware architectures for electronic and embedded systems. The emphasis is on methods, algorithms, and tools related to the use of computers in designing complete systems. The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.

Track Chair: Lejla Batina, Radboud University, NL

Topics

D1 System Specification and Modelling

Chair: Gianluca Palermo, Politecnico di Milano, IT

Co-Chair: Julio Medina, University of Cantabria, ES

Topic Members

• Rainer Doemer, EECS, UC Irvine, US
• Abdoulaye Gamatie, CNRS LIRMM / University of Montpellier, FR
• Matthias Jung, Fraunhofer IESE, DE
• Laurence Pierre, Univ. Grenoble Alpes, TIMA Lab., FR
• Todor Stefanov, Leiden University, NL
• Min Zhang, East China Normal University, CN

Modeling and specification methodologies for complex HW-SW systems; requirements engineering; multi-domain/multi-criteria specifications; meta-modeling; design and specification languages; application and workload models; models of computation and their (static) analysis; models of concurrency and communication; model- and component-based design; refinement and validation flows; modeling and analysis of functional and non-functional system properties; modeling of system adaptivity; time and performance modeling; predictive and learning-based models; system-level platform and architecture models and simulation; heterogeneous system models.

D2 System-Level Design Methodologies and High-Level-Synthesis

Chair: Philippe Coussy, Universite de Bretagne-Sud / Lab-STICC, FR

Co-Chair: Christian Pilato, Politecnico di Milano, IT

Topic Members

• Lars Bauer, Karlsruhe Institute of Technology, DE
• Alberto Antonio Del Barrio Garcia, Complutense University of Madrid, ES
• Dionysios Diamantopoulos, IBM Research, CH
• Yuko Hara-Azumi, Tokyo Institute of Technology, JP
• Lana Josipovic, ETH Zurich, CH
• Dirk Koch, University of Manchester, GB
• Luciano Lavagno, Politecnico di Torino, IT
• Razvan Nane, TU Delft, NL
• Stephen Neuendorffer, Xilinx, US
• David Novo, CNRS, LIRMM, University of Montpellier, FR
• Preeti Ranjan Panda, Indian Institute of Technology, Delhi, IN
• Wei Zhang, Hong Kong University of Science and Technology, HK

High-level and system-level synthesis techniques; high-level languages for system and behavioral descriptions; system-level models for design and optimization; methods for HW-SW co-design and partitioning; HW-SW interface and protocol communication synthesis; interface-based and correct-by-construction designs; control and data flow analysis; high-level and system-level scheduling, allocation, and binding techniques; design space exploration and systematic optimization techniques for high-level synthesis and system-level design; platform-based and reuse-centric design methods and architectures, including accelerator-rich architectures; HW/SW design patterns for multi-processor system-on-chip (MPSoC); system-level design of heterogeneous computing systems; high-level synthesis and system-level design for machine-learning applications.

D3 System Simulation and Validation

Chair: Katell Morin-Allory, TIMA Laboratory, FR

Co-Chair: Monica Farkash, AMD, US

Topic Members

• Mingsong Chen, East China Normal University, CN
• Masahiro Fujita, University of Tokyo, JP
• Tiziana Margaria, University of Limerick and Lero, IE
• Jaan Raik, Tallinn University of Technology, EE
• Shobha Vasudevan, UIUC, US
• Avi Ziv, IBM Research - Haifa, IL

Simulation-based and semi-formal validation and verification of SoCs, cyber-physical systems and emerging architectures at any level, from system to circuit, including, in particular, testbench and assertion generation and qualification, coverage metrics for functional validation and verification, checker synthesis and optimization, multi-domain and mixed-critical simulation techniques, acceleration-driven and emulation-based approaches for verification and validation, simulation-based pre- and post-silicon debugging, validation and verification for IoT and cloud infrastructures and semi-formal methods for security verification and detection of vulnerabilities, with or without the employment of artificial intelligence or machine learning techniques.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Rosa Rodríguez-Montañés, UPC, ES

Co-Chair: Helmut Graeb, Technical University of Munich, DE

Topic Members

• Günhan Dündar, Bogazici University, TR
• William Eisenstadt, University of Florida, US
• Jiun-Lang Huang, National Taiwan University, TW
• Mahfuzul Islam, Kyoto University, JP
• Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
• Linda Milor, Georgia Tech, US
• Shahriar Mirabbasi, University of British Columbia, CA
• Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Nele Mentens, KU Leuven, BE

Co-Chair: Kazuo Sakiyama, The University of Electro-Communications, JP

Topic Members

• Ileana Buhan, Radboud University, NL
• Milos Drutarovsky, Technical University of Kosice, SK
• Fatemeh Ganji, Worcester Polytechnic Institute, US
• Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
• Mike Hutter, Cryptography Research Inc., US
• Stjepan Picek, TU Delft, NL
• Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
• Johanna Sepúlveda, Airbus Defence and Space, DE
• Dai Yamamoto, Fujitsu Limited, JP
• Bohan Yang, Tsinghua University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modeling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Topic Members

• Josep Balasch, KU Leuven, BE
• Lejla Batina, Radboud University Nijmegen, NL
• Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
• Elke De Mulder, Rambus, Cryptography Research Division, FR
• Giorgio Di Natale, TIMA, FR
• Junfeng Fan, Open Security Research, Inc., CN
• Apostolos Fournaris, Industrial Systems Institute/Research Center ATHENA, GR
• Samaneh Ghandali, Google, US
• Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
• Johann Heyszl, Fraunhofer AISEC, DE
• Elif Bilge Kavun, University of Passau, DE
• Osnat Keren, Bar-Ilan University, IL
• Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
• Martin Novotny, Czech Technical University in Prague, CZ
• Patrick Schaumont, Worcester Polytechnic Institute, US
• Tobias Schneider, NXP Semiconductors, AT
• Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

D7 Formal Methods and Verification

Chair: Anna Slobodova, Centaur Technology, US

Co-Chair: Yakir Vizel, The Technion, IL

Topic Members

• Ivana Černá, Masaryk University, CZ
• Alexander Nadel, Intel, IL
• Stefano Quer, Politecnico di Torino, IT
• Heinz Riener, Cadence Design Systems, DE
• Georg Weissenbacher, Vienna University of Technology, AT

Formal models of software and hardware systems; formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction, techniques and compositional reasoning); core algorithmic technologies supporting formal verification such as SAT and SMT techniques; formal verification of hardware (including IPs, SoCs, and cores), software, HW-SW systems, timed, or hybrid systems; semi-formal verification techniques; integration of verification into design flows; challenges of multi-cores (as verification targets or as verification host platforms); formal synthesis; formal methods in emerging technologies.

D8 Network-on-Chip and On-Chip Communication

Chair: Romain Lemaire, CEA-List, FR

Co-Chair: Li-Shiuan Peh, Professor, National University of Singapore, SG

Topic Members

• Jose L. Abellan, Universidad Católica San Antonio de Murcia, ES
• Kees Goossens, Eindhoven university of technology, NL
• John Kim, KAIST, KR
• Pierre-Axel Lagadec, Atos, FR
• Sébastien Le Beux, Concordia University, CA
• Fernando Moraes, PUCRS University, BR
• Pengju Ren, Xi'an Jiaotong University, CN
• Hamid Sarbazi-Azad, Sharif U of Tech, IR
• Davide Zoni, Politecnico di Milano, IT

Architecture, design methodologies, modeling and simulation techniques for intra- and inter-chip interconnects, network-on-chip and on-chip communication infrastructure, including, but not limited to, topology, routers, interfaces, flow control, quality of service, security, reliability, design space exploration frameworks, on-chip communication specifications and programming models for communication-centric design. Contributions from specific applicative domains are welcomed such as interconnects for high-performance computing, in- or near-memory computing, machine-learning, artificial intelligence accelerators. The topic also covers the design of on-chip communication infrastructures with technological constraints (FPGA, interposer/chiplet for 2.5D, 3D, photonics, non-volatile memory…)

D9 Architectural and Microarchitectural Design

Chair: Olivier Sentieys, INRIA, FR

Co-Chair: Jeronimo Castrillon, TU Dresden, DE

Topic Members

• Francisco J Cazorla, Barcelona Supercomputing Center, ES
• Caroline Collange, Inria, FR
• Pedro Diniz, INESC-ID, PT
• Zhenman Fang, Simon Fraser University, CA
• Paula Herber, University of Münster, DE
• Christophe Jego, IMS Labo, Bordeaux INP, FR
• Alexandra Jimborean, University of Murcia, ES
• Alex Jones, University of Pittsburgh, US
• Lei Ju, School of Cyber Science and Technology, Shandong University, CN
• Georgios Keramidas, Aristotle University of Thessaloniki/Think Silicon S.A., GR, GR
• Leonidas Kosmidis, Universitat Politècnica de Catalunya - Barcelona Supercomputing Center, ES
• Tanguy Risset, Univ Lyon, INSA Lyon, Inria, CITI, FR
• Cristina Silvano, Politecnico di Milano, IT
• Sharad Sinha, Indian Institute of Technology (IIT) Goa, IN
• Magnus Själander, Norwegian University of Science and Technology, NO
• Chundong Wang, ShanghaiTech University, CN

Architectural and microarchitectural design techniques, including: memory systems; architectural methods for improving power and energy efficiency; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for timing predictability.

D10 Low-power, Energy-efficient and Thermal-aware Design

Chair: Pascal Vivet, CEA-Leti, FR

Co-Chair: Masanori Hashimoto, Kyoto University, JP

Topic Members

• Sylvain Clerc, STMicroelectronics, FR
• Shao-Yun Fang, National Taiwan University of Science and Technology, TW
• William Fornaciari, Politecnico di Milano - DEIB, IT
• Alberto Macii, Politecnico di Torino, IT
• Sebastien Pillement, Polytech Nantes - IETR, FR
• Davide Rossi, University Of Bologna, IT
• Youngsoo Shin, KAIST, KR
• Rene van Leuken, Delft University of Technology, NL
• Daniel Wong, University of California, Riverside, US
• Grace Li Zhang, Technical University of Munich, DE
• Cheng Zhuo, Zhejiang University, CN

Theories, tools, methodologies and circuit-level structures to implement electronic circuits and systems with low power consumption, high energy efficiency, and correct thermal behavior. These can be applied to a full range of applications, from ultra-low power systems (e.g. for portable/wearable applications at the edge of the IoT) to large-scale battery systems (electric vehicles, energy storage systems) and high-performance systems (data-centers and cloud computing). Topics of interest include: thermal/power monitors and knobs at circuit level; hardware/software cross-layer optimizations, with emphasis on power modeling and optimization; temperature modeling and prediction; thermal-power-aware optimization; energy-aware design, battery-aware design, including energy efficiency optimization for application specific designs (e.g. AI, ML, etc.); smart management of heterogeneous energy-sources; energy harvesting for cyber-physical systems.

D11 Approximate Computing

Chair: Lukas Sekanina, Brno University of Technology, CZ

Co-Chair: Jie Han, University of Alberta, CA

Topic Members

• Mario Barbareschi, University of Naples Federico II, IT
• Nikolaos Bellas, University of Thessaly, GR
• Nikil Dutt, University of California Irvine, US
• Honglan Jiang, Tsinghua University, CN
• Oliver Keszocze, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
• Weiqiang Liu, Nanjing University of Aeronautics and Astronautics, CN
• Daniel Menard, INSA Rennes, FR
• Veljko Pejovic, University of Ljubljana, SI
• Laura Pozzi, USI Lugano, CH
• Lan Wei, University of Waterloo, CA

Design techniques enabling and supporting approximate computing at all levels of the computer stack: circuit, architecture, memory, operating system and software level; top-down and bottom-up approaches; cross-level approximation; quality analysis of approximate systems; dynamic approximation; design automation tools for approximate computing and their benchmarking.

D12 Reconfigurable Systems

Chair: Suhaib A. Fahmy, KAUST, SA

Co-Chair: Michaela Blott, Xilinx, IE

Topic Members

• Christos Bouganis, Imperial College London, GB
• Nachiket Kapre, University of Waterloo, CA
• Miriam Leeser, Northeastern University, US
• Bogdan Pasca, Intel, FR
• Thomas Preußer, Accemic Technologies, DE
• David Sidler, Microsoft Corporation, CH
• Ioannis Sourdis, Chalmers University of Technology, SE
• Daniel Ziener, Technische Universität Ilmenau, DE

Reconfigurable computing platforms and architectures; heterogeneous platforms (e.g., including FPGA/GPU/CPU); reconfigurable processors; statically and dynamically reconfigurable systems and components; reconfigurable computing for machine learning, data center and high-performance computing; FPGA architecture; FPGA partial reconfiguration; design methods and tools for reconfigurable computing.

D13 Logical and Physical Analysis and Design

Chair: L. Miguel Silveira, INESC ID/IST - Lisbon University, PT

Co-Chair: Mathias Soeken, Microsoft, CH

Topic Members

• Laleh Behjat, University of Calgary, CA
• Luca Daniel, M.I.T., US
• Alper Demir, Koc University, TR
• Elena Dubrova, Royal Institute of Technology - KTH, SE
• Petr Fišer, Czech Technical University in Prague, FIT, CZ
• Igor L. Markov, University of Michigan, US
• Mayler Martins, Mentor Graphics, US
• Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
• Eleonora Testa, Synopsys Inc., CH
• Tiziano Villa, Università di Verona, IT
• Nina Yevtushenko, Ivannikov institute for system programming of RAS, RU

Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; logic synthesis for emerging technologies; combined logic synthesis and layout design and characterization; statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automated place-and-route; interconnect- and performance-driven layout; process technology developments; parasitic and variation-aware extraction for on-chip interconnect and passives; macro-modeling, behavioral and reduced order modeling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground, and substrate.

D14 Emerging Design Technologies for Future Computing

Chair: Elena Gnani, University of Bologna, IT

Co-Chair: Gage Hills, Harvard University, US

Topic Members

• Mohamed M. Sabry Aly, Nanyang Technological University, SG
• Veeresh Deshpande, Helmholtz Zentrum Berlin, DE
• Vihar Georgiev, University of Glasgow, GB
• Qianqian Huang, Peking University, CN
• Heike Riel, IBM Research, CH
• Alessio Spessot, Imec, BE
• Victor Sverdlov, CDL NovoMemLog IuE TUWien, AT
• Aida Todri-Sanial, LIRMM, University of Montpellier, CNRS, FR
• Tony Wu, Facebook, US
• Shimeng Yu, Georgia Institute of Technology, US

Modeling, circuit design, and design automation flows for future computing, including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (including TSV modeling and design space exploration).

D15 Emerging Design Technologies for Future Memories

Chair: Shahar Kvatinsky, Technion, IL

Co-Chair: Damien Querlioz, Univ Paris-Sud, FR

Topic Members

• Rajendra Bishnoi, Delft University of Technology, NL
• Joseph Friedman, The University of Texas at Dallas, US
• Xiaotao Jia, School of Microeletronics, Beihang University, CN
• Alexandre Levisse, EPFL, CH
• Rawan Naous, KAUST, SA
• Jean-Philippe Noel, CEA, FR
• Mengying Zhao, Shandong University, CN

Modeling, circuit design, and design automation flows for future data storage systems, including non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots, etc.); memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile caches etc.); memory management techniques for emerging memories.

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Track A: Application Design

is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, real-world implementations, and applications of specific design and test methodologies. Contributions should illustrate innovative or record-breaking designs, which will provide viable solutions in tomorrow’s silicon, embedded systems, and large-scale systems. In topic A8, there is the opportunity to submit 2-page papers that expose industrial research and practice.

Track Chair: Theocharis Theocharides, University of Cyprus, CY

Topics

A1 Power-efficient and Sustainable Computing

Chair: Andreas Burg, EPFL-TCL, CH

Co-Chair: Jungwook Choi, Hanyang University, KR

Topic Members

• Andrea Bartolini, University of Bologna, IT
• Thidapat (Tam) Chantem, Virginia Tech, US
• Mingu Kang, University of Illinois at Urbana Champaign, US
• Saibal Mukhopadhyay, Georgia Institute of Technology, US
• Qinru Qiu, Syracuse University, US
• Semeen Rehman, TU Wien, AT
• Amit Kumar Singh, University of Essex, GB
• Georgios Zervakis, Karlsruhe Institute of Technology, DE

Application design experiences and real implementations of power-efficient systems or circuits with high industrial relevance or high environmental impact, especially targeting ultra-low-power, high-performance, or large-scale computing systems (such as MPSoCs, mobile systems, massively parallel computers, 2D/3D multi-/many-core systems, high-performance computing clusters, data centers, and cloud systems). Topics of interest include: software architectures for energy-efficient computing; virtualization; energy-efficient memory; low-power processors; emerging communication or computing systems (e.g., power-efficient machine learning accelerators); in-memory computing or memristor-based accelerators; heterogeneous computing; resource management techniques; innovative data-center management strategies; SW/OS-level implementations in real systems and data centers; energy-efficient big data management; data centers powered by renewable energy sources and data centers in smart grids.

A2 Smart Cities, Internet of Everything, Industry 4.0

Chair: Saraju Mohanty, University of North Texas, US

Co-Chair: Fabrizio Lamberti, Politecnico di Torino, IT

Topic Members

• Franco Fummi, Università di Verona, IT
• Michael Huebner, Brandenburg Technical University Cottbus, DE
• Srinivas Katkoori, University of South Florida, US
• Christos Kyrkou, University of Cyprus, CY
• Kamalakanta Mahapatra, NIT Rourkela, INDIA, IN

Applications, design experiences and real-life implementations of theory, design, construction, manufacture and/or end-use of mass market electronics, systems, software, and services for smart cities, smart industries, smart homes, smart consumer electronics, Internet of Things (IoT), and Internet-of-Everything (IoE). Topics of interest include: smart and sustainable mobility; smart transportation; smart economy; smart environment (including street cleaning, water management, water supply, air quality monitoring, disposal facilities, lighting, etc.). Other topics of interest are the verticals of IoT, IoE, Industry 4.0, Consumer Electronics, smart home, and smart cities including: smart wearables; robotic systems for smart cities and smart homes; smart sensors; blockchain technology; video technology; audio technology; white goods; home care products; mobile communications; gaming; air care products; home automation and networking devices; home theater; digital imaging; in-vehicle technology; cable & satellite technology; home security; domestic lighting; human interface; consumer storage technology; AI/ML techniques for these smart systems; energy-management techniques for these systems; security-privacy techniques for these systems.

A3 Automotive Systems and Smart Energy Systems

Chair: Selma Saidi, Technische Universität Dortmund, DE

Co-Chair: Michele Magno, ETH Zürich, CH

Topic Members

• Donkyu Baek, Chungbuk National University, KR
• Domenico Balsamo, Newcastle University, GB
• Davide Brunelli, University of Trento, IT
• Lulu Chan, NXP Semiconductors, NL
• Dip Goswami, Eindhoven University of Technology, NL
• Dirk Ziegenbein, Robert Bosch GmbH, DE

Design experiences for automotive systems, autonomous robotics and UAV , energy-neutral embedded systems, smart energy systems (from uW to microgrid) and energy efficient smart sensors, and related Cyber-Physical applications.
Topics of interest include: transient computing; energy harvesting circuits, smart energy systems, and embedded platforms with particular interest in energy efficient intelligent system ; MEMS; integrated sensors and transducers; machine learning on microcontrollers and low power processors, RF architectures; innovative concepts for power distribution, energy storage, grid monitoring and high-voltage structures; solutions for runtime system management such as self-diagnostics and repair; design and optimization of energy generation and renewable energy subsystems; smart autonomus algorithms and systems for electric vehicles and unmanned aerial vehicle; in-vehicle networks and system architectures; optimization of system energy efficiency in the context of automotive or smart energy applications.

A4 Augmented Living and Personalized Healthcare

Chair: Marina Zapater, University of Applied Sciences Western Switzerland (HES-SO), CH

Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler (FBK), IT

Topic Members

• Amir Aminifar, Lund University, SE
• Simone Benatti, University of Bologna, IT
• Guillermo Botella, Complutense University of Madrid, ES
• Andrea Cossettini, ETH Zürich, CH
• Eduardo de la Torre, Technical University of Madrid, ES
• Amir M. Rahmani, University of California Irvine, US

Design experiences covering the use of body area networks, assistive and wearable technologies, robot-assisted living and healthcare, edge computing and IoT for healthcare, wellness and augmented living. Topics of interest include: technologies, devices, systems and paradigms (including approximate or significance-driven computing) for ultra-low/zero power systems for personal health and personalized medicine including non-intrusive or implantable miniaturized sensors and actuators, on-board performance optimization and contextualized power-management ; embedded IP and systems for audio, video, and computer vision domains ; intelligent sensor networks, systems, automation and environments for augmented living, assisted living, rehabilitation, healthcare and wellness ; embedded and edge-based machine learning for augmented living.

A5 Secure Systems, Circuits, and Architectures

Chair: Pascal Benoit, University of Montpellier, FR

Co-Chair: Bertrand Cambou, Northern Arizona University, US

Topic Members

• Aydin Aysu, North Carolina State University, US
• M. Khurram Bhatti, Information Technology University (ITU), PK
• Begul Bilgin, Rambus Cryptography Research, NL
• Ray Cheung, City University of Hong Kong, HK
• Fabrizio De Santis, Siemens AG, DE
• Julien Francq, Naval Group, FR
• Kris Gaj, George Mason University, US
• Bogdan Groza, Politehnica Unviersity Timisoara, RO
• Basel Halak, Southampton University, GB
• David Hély, Univ. Grenoble Alpes, Grenoble INP, LCIS, FR
• Michail Maniatakos, New York University Abu Dhabi, AE
• Samuel Pagliarini, Tallinn University of Technology (TalTech), EE
• Guilherme Perin, Delft University of Technology, NL
• Nicolas Sklavos, Computer Engineering & Informatics Department, University of Patras, GR

Secure circuits and architectures, with an emphasis on design experiences, real system deployments, applications, and silicon prototypes. Topics of interest include: secure HW architectures; hardware architectures for post quantum cryptography; emerging technologies for secure circuits and architectures, novel architectures for embedded cryptography; demonstrations with fault or other physical attacks; embedded processors or co-processors for security; off-chip memories and network-on-chip and secure communication/integrity; demonstrations of HW-enabled security on real systems or prototypes; logic-level security; firmware security.

A6 Self-adaptive and Context-aware Systems

Chair: Geoff Merrett, University of Southampton, GB

Co-Chair: Andy Pimentel, University of Amsterdam, NL

Topic Members

• Woongki Baek, UNIST, KR
• Giovanni Beltrame, Polytechnique Montreal, CA
• Heba Khdr, Karlsruhe Institute of Technology, DE
• Anne Liret, British Telecom (BT), FR
• Antonio Carlos Schneider Beck, Universidade Federal do Rio Grande do Sul, BR
• Stefanos Skalistis, United Technologies Research Centre, IE

Self-adaptive and context-aware systems for run-time decision-making. This includes systems and algorithms targeting various optimization goals such as compute performance, energy/power-efficiency or reliability and considering various architectural platforms, such as high-performance compute nodes, power-constrained edge computing technologies and reconfigurable systems. Such approaches may utilise machine learning techniques to achieve the desired behaviour. Topics of interests include, but are not limited to, adaptive strategies for runtime resource management; prediction/forecasting and control of self-adaptive systems, for example using machine learning techniques for offline and/or online modelling; adaptive systems and/or algorithms which can adapt their operation based on available resources, external contexts, etc; application of diverse data mining, modeling and optimization techniques for adaptive systems (control automation, game theory, etc.); design experiences and industrial use-cases of self-adaptive systems.

A7 Applications of Emerging Technologies

Chair: Michael Niemier, University of Notre Dame, US

Co-Chair: Bastien Giraud, CEA LETI, FR

Topic Members

• Mirela Alistar, University of Colorado Boulder, US
• Kerem Camsari, University of California, Santa Barbara, US
• Anupam Chattopadhyay, Nanyang Technological University, SG
• Giovanni Finocchio, University of Messina, IT
• Andreas Fuhrer Janett, IBM Research, CH
• Said Hamdioui, Delft University of Technology, NL
• Giulia Meuli, Synopsys, IT
• Vasilis Pavlidis, University of Manchester, GB
• Sudip Poddar, Johannes Kepler University, AT
• Frank Sill Torres, German Aerospace Center, DE
• Elena Ioana Vatajelu, TIMA, FR
• Elisa Vianello, CEA Leti, FR
• Shigeru Yamashita, Ritsumeikan University, JP
• Xunzhao Yin, Zhejiang University, CN

Applications of and design methods for systems based on future and emerging technologies. Topics of interest include: neuromorphic and bio-inspired computing systems; bio-MEMS and lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical systems, etc.).

A8 Industrial Experiences Brief Papers

Chair: Christian Weis, University of Kaiserslautern, DE

Co-Chair: Nicolas Ventroux, THALES RESEARCH & TECHNOLOGY, FR

Topic Members

• Mohamed Ibrahim, University of California, Berkeley, US
• Dionisios Pnevmatikatos, School of ECE, National Technical University of Athens & FORTH-ICS, GR
• Wenjing Rao, University of Illinois at Chicago, US

Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

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Track T: Test and Dependability

covers all test, design for test, reliability, and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analogue and digital electronics. Topics of interest also include diagnosis, failure mode analysis, debug and post-silicon validation challenges, and test or fault injection methods addressing system security.

Track Chair: Ilia Polian, University of Stuttgart, DE

Topics

T1 Modelling and Mitigation of Defects, Faults, Variability, and Reliability

Chair: Arnaud Virazel, LIRMM, FR

Co-Chair: Bram Kruseman, NXP Semiconductors, NL

Topic Members

• Daniel Arumi, UPC, ES
• Leticia Maria Bolzani Poehls, RWTH Aachen University, DE
• Yuanqing Cheng, Beihang University, CN
• Naghmeh Karimi, University of Maryland Baltimore County, US
• Christian Sauer, Cadence Design Systems, DE
• Matteo Sonza Reorda, Politecnico di Torino - DAUIN, IT
• Mottaqiallah Taouil, Delft University of Technology, NL
• Hank Walker, Texas A&M University, US

Identification, characterization, and modeling of defects, faults, and degradation mechanisms in conventional, advanced, or emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT, etc.); defect-based fault analysis; reliability analysis and modeling at device, circuit, or component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit or component level.

T2 Test Generation, Test Architectures, Design for Test, and Diagnosis

Chair: Maria K. Michael, Electrical and Computer Engineering & KIOS Center of Excellence, University of Cyprus, CY

Co-Chair: Grzegorz Mrugalski, Mentor Graphics, PL

Topic Members

• Paolo Bernardi, Politecnico di Torino, IT
• Sybille Hellebrand, University of Paderborn, DE
• Chrysovalantis Kavousianos, Department of Computer Science and Engineering, University of Ioannina, GR
• Teresa McLaurin, ARM, US
• Melanie Schillinsky, NXP Germany GmbH, DE
• Xiaoqing Wen, Kyushu Institute of Technology, JP

Test pattern generation for logic and delay faults, defect-based fault models, low-power ICs; fault simulation; test compression; power/thermal issues in test; test generation and test architectures for memories, FPGAs, microprocessors, accelerators, NoC, SoC and 3D ICs; solutions for design-for-test, diagnosis, machine learning for IC testing; BIST; board and system test; volume diagnosis and yield analysis.

T3 Dependability and System-Level Test

Chair: Karthik Pattabiraman, University of British Columbia, CA

Co-Chair: Stefano Di Carlo, Politecnico di Torino, IT

Topic Members

• Dimitris Gizopoulos, University of Athens, GR
• Angeliki Kritikakou, Univ Rennes, Inria, CNRS, IRISA, FR
• Michael Paulitsch, Intel, DE
• Juan Carlos Ruiz Garcia, Universitat Politecnica de Valencia, ES
• Rishad Shafik, Newcastle University, GB
• Radha Venkatagiri, Oregon State University, US

HW and SW solutions for system’s dependability crossing all layers of the system’s stack: microarchitecture-level and system-level error/fault modeling; cross-layer dependability analysis and evaluation; reliable and fail-safe architectures and systems design; system-level on-line test and functional safety; runtime system management for dependability; cross-layer solutions for dependability (microarchitecture-level, software-level, system-level); application resilience; high-level synthesis (HLS) dependability, approximate computing for resilient systems, computational intelligence methods (AI/ML) for dependability; system-level and microarchitecture-level solutions for safety- and mission-critical systems, IoT and cloud infrastructures.

DT4 Design and Test for Analog and Mixed-Signal Circuits and Systems, and MEMS

Chair: Rosa Rodríguez-Montañés, UPC, ES

Co-Chair: Helmut Graeb, Technical University of Munich, DE

Topic Members

• Günhan Dündar, Bogazici University, TR
• William Eisenstadt, University of Florida, US
• Jiun-Lang Huang, National Taiwan University, TW
• Mahfuzul Islam, Kyoto University, JP
• Gildas Leger, Instituto de Microelectronica de Sevilla, IMSE-CNM, (CSIC - Universidad de Sevilla), ES
• Linda Milor, Georgia Tech, US
• Shahriar Mirabbasi, University of British Columbia, CA
• Haralampos-G. Stratigopoulos, Sorbonne Université, CNRS, LIP6, FR

Analog and mixed-signal architecture, system and circuit synthesis and optimization; formal methods and symbolic techniques; layout synthesis and topology generation; HW description languages and models of computation; innovative circuit topologies and architectures; analog and mixed-signal IC design; MEMS; design for manufacturability and design for yield; design for reliability; self-healing and self-calibration; test generation; fault modeling and simulation; design for testability; built-in self-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; test metrics and economics.

DT5 Design and Test of Hardware Security Primitives

Chair: Nele Mentens, KU Leuven, BE

Co-Chair: Kazuo Sakiyama, The University of Electro-Communications, JP

Topic Members

• Ileana Buhan, Radboud University, NL
• Milos Drutarovsky, Technical University of Kosice, SK
• Fatemeh Ganji, Worcester Polytechnic Institute, US
• Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
• Mike Hutter, Cryptography Research Inc., US
• Stjepan Picek, TU Delft, NL
• Ahmad-Reza Sadeghi, Technische Universitaet Darmstadt, DE
• Johanna Sepúlveda, Airbus Defence and Space, DE
• Dai Yamamoto, Fujitsu Limited, JP
• Bohan Yang, Tsinghua University, CN

Hardware security primitives, including (post-quantum) cryptographic circuits; side-channel analysis (including modeling, verification and simulation); fault injection attacks; physically unclonable functions (PUF) and true random number generators (TRNG), AI methods in hardware security.

DT6 Design and Test of Secure Systems

Chair: Francesco Regazzoni, University of Amsterdam and ALaRI - USI, CH

Co-Chair: Ricardo Chaves, INESC-ID, IST, Universidade de Lisboa, PT

Topic Members

• Josep Balasch, KU Leuven, BE
• Lejla Batina, Radboud University Nijmegen, NL
• Shivam Bhasin, Temasek Laboratories, Nanyang Technological University, SG
• Elke De Mulder, Rambus, Cryptography Research Division, FR
• Giorgio Di Natale, TIMA, FR
• Junfeng Fan, Open Security Research, Inc., CN
• Apostolos Fournaris, Industrial Systems Institute/Research Center ATHENA, GR
• Samaneh Ghandali, Google, US
• Annelie Heuser, Univ Rennes, Inria, CNRS, IRISA, FR
• Johann Heyszl, Fraunhofer AISEC, DE
• Elif Bilge Kavun, University of Passau, DE
• Osnat Keren, Bar-Ilan University, IL
• Debdeep Mukhopadhyay, Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, IN
• Martin Novotny, Czech Technical University in Prague, CZ
• Patrick Schaumont, Worcester Polytechnic Institute, US
• Tobias Schneider, NXP Semiconductors, AT
• Ruggero Susella, STMicroelectronics, IT

Design-for-trust (secure design methods); Test infrastructures for secure devices; Trusted manufacturing; Counterfeit detection and avoidance; Design, test and automation (for HW tampering attacks and protection, for Countermeasures, for Side-channel protection verification, for Fault protection verification); Microarchitectural attacks; HW trojans (attacks, detection, or countermeasures); Machine learning for the above topics, Side-channel attacks on machine learning and counter measures.

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Track E: Embedded Systems Design

is devoted to the modelling, analysis, design and deployment of embedded software or embedded/cyber-physical systems. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on model-based design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked systems, and dependable systems.

Track Chair: Liliana Cucu, Inria, FR

Topics

E1 Embedded Software Architecture, Compilers and Tool Chains

Chair: Sara Vinco, Politecnico di Torino, IT

Co-Chair: Sudipta Chattopadhyay, Singapore University of Technology and Design (SUTD), SG

Topic Members

• Urbi Chatterjee, Indian Institute of Technology Kanpur, IN
• Christian Fabre, CEA LIST, FR
• Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE
• Michele Lora, University of Southern California, US
• Hiren Patel, University of Waterloo, CA
• Eduardo Quinones, Barcelona Supercomputing Center, ES
• Ahmed Rezine, Linköping University, SE
• Marjan Sirjani, Mälardalen University, SE
• Yi Wang, Shenzhen University, CN

Software architectures, programming paradigms, languages, compiler support, software tools, and techniques (e.g., simulators, synthesis tools) targeting embedded heterogeneous systems for domain-specific applications such as IoTs and wearables; embedded software support for approximate computation and FPGA/GPU based accelerators; memory communication protocols and hierarchy management, including caches, scratchpad, and non-volatile memories; code analysis, code optimization/generation to enhance performance, power/energy, code/data size, reliability, security, WCET, etc.; real-time software, distributed system software, virtualization, and middleware for embedded systems, including resource-awareness, reconfiguration, energy/power management; compiler support for enhanced debugging, profiling, and traceability.

E2 Real-time, Dependable and Privacy-Enhanced Systems

Chair: Marko Bertogna, University of Modena, IT

Co-Chair: Mitra Nasri, Eindhoven University of Technology, NL

Topic Members

• Gedare Bloom, University of Colorado Colorado Springs, US
• Arvind Easwaran, Nanyang Technological University, SG
• Julien Forget, Univ. Lille, FR
• Leandro Indrusiak, University of York, GB
• Hyoseung Kim, University of California, Riverside, US
• Renato Mancuso, Boston University, US
• Geoffrey Nelissen, Eindhoven University of Technology, NL
• Elena Troubitsyna, KTH -- Royal Institute of Technology, SE

Real-time performance modeling, analysis and empirical evaluation; worst-case performance analysis techniques; real-time schedulability of multicore systems; use of hardware virtualization techniques in time-critical applications; power-aware real-time systems; industrial case studies of real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; security attack protection and analysis of embedded systems' hardware and software; privacy-enhanced and safety-enhanced systems; network control and QoS for embedded applications.

E3 Machine Learning Solutions for Embedded and Cyber-Physical Systems

Chair: Luca Carloni, Columbia University, US

Co-Chair: Mario R. Casu, Politecnico di Torino, Department of Electronics and Telecommunications, IT

Topic Members

• Mladen Berekovic, Universität zu Lübeck, DE
• Anup Das, Drexel University, US
• Georgi Gaydadjiev, Maxeler / Imperial College, GB
• Diana Goehringer, TU Dresden, DE
• Cong Hao, Georgia Institute of Technology, US
• Axel Jantsch, TU Wien, AT
• Kyuho Lee, UNIST, KR
• Jan Madsen, Technical University of Denmark, DK
• Smail Niar, Université Polytechnique Hauts-de-France, FR
• Andrés Otero, Universidad Politécnica de Madrid, ES
• Alessandro Pinto, Raytheon Technologies Research Center, US
• Abbas Rahimi, IBM Research, CH
• Sander Stuijk, Eindhoven University of Technology, NL
• Li-Rong Zheng, Fudan University, CN

Hardware architectures, software and algorithmic approaches for artificial intelligence, machine learning and deep learning solutions; specialized, heterogeneous, and resource-efficient embedded architectures for machine learning; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; case studies of machine learning applications implemented on embedded systems and cyber physical systems.

E4 Design Methodologies for Machine Learning Architectures

Chair: Tushar Krishna, Georgia Institute of Technology, US

Co-Chair: Marian Verhelst, KU Leuven, BE

Topic Members

• Giovanni Ansaloni, EPFL, CH
• José Cano, University of Glasgow, GB
• Francesco Conti, University of Bologna, IT
• Henk Corporaal, TU/e (Eindhoven University of Technology), NL
• Steve Dai, NVIDIA, US
• Jonas Doevenspeck, imec, BE
• Giulio Gambardella, Synopsys, IE
• Weiwen Jiang, George Mason University, US
• Jan Moritz Joseph, RWTH Aachen University, DE
• Steven Latre, University of Antwerp - IMEC, BE
• Huichu Liu, Facebook Inc., US
• Bert Moons, Qualcomm, NL
• Miguel Peón Quirós, EPFL ESL, CH
• Priyanka Raina, Stanford University, US
• Brandon Reagen, NYU/Facebook, US
• Jae-sun Seo, Arizona State University, US
• Swagath Venkataramani, IBM T. J. Watson Research Center, US

Design methodologies, optimizations, verification, analysis and reliability for machine learning architectures. Specializiations, and resource-efficient optimizations for machine learning architectures; embedded architectures and software for autonomy, automated reasoning, and planning algorithms; approximate architectures for machine learning applications; learning from limited data sets; frameworks for probabilistic and deep learning programming; safe and secure machine learning; novel neural networks architectures and concepts for embedded computing.

E5 Design Modelling and Verification for Embedded and Cyber-Physical Systems

Chair: Davide Quaglia, Università di Verona, IT

Co-Chair: Mohammad Al Faruque, University of California Irvine, US

Topic Members

• Christel Baier, TU Dresden, DE
• Khaza Anuarul Hoque, University of Missouri, US
• Martin Horauer, University of Applied Sciences Technikum Wien, AT
• Wenchao Li, Boston University, US
• Chung-Wei Lin, National Taiwan University, TW
• Pierluigi Nuzzo, University of Southern California, US
• Roberto Passerone, University of Trento, IT

Modeling, design, verification, validation and optimization of embedded systems and Cyber-Physical Systems (CPS) including large-scale and networked CPS as in current Internet-of-Things as well as software-intensive CPS; modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, quality-of-service, safety and reliability; theories, languages and tools supporting model-based design flows covering software, control and physical components; verification techniques ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods as well as monitoring and runtime verification; data-mining and CPS, autonomous CPS, networked and switched control systems (e.g. control/architecture co-design and architecture-aware controller synthesis); cognitive control for CPS and socio-technical systems (e.g. empowered consumer and organizational behavior in smart grids).

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