Workshop Description

3D technologies are becoming more and more pervasive in digital architectures, as a strong enabler for heterogeneous integration. Due to the high amount of required data and associated memory capacity, Machine Learning and AI accelerator could benefit of 3D integration not only for High Performance Computing (HPC), but also for the edge and embedded HPC. 3D integration and associated architectures are opening a wide spectrum of system solutions, from chiplet-based partitioning for High Performance Computing to various sensors such as fully integrated image sensors embedding AI features, but also with the tight 3D coupling of computing & memory enabling efficient In-Memory-Computing paradigm.

The goal of the 3D Integration Workshop is to bring together experts from both academia and industry, interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

This one-day event consists of two keynotes, and four sessions, with invited presentations and submitted presentations. Previous editions of this workshop took place regularly, in conjunction with early editions of DATE conferences.

Workshop Committee

• General co-Chairs:
  • P. Vivet, CEA-LIST, IRT Nanoelec (FR)
  • M. Badaroglu, Qualcomm (BE)
• Program co-Chairs :
  • P. Ramm, Fraunhofer EMFT (GE)
  • S. Mukhopadhyay, Georgia Tech (USA)
• Special Session Chair
  • S. Mitra, Stanford University (USA)
• Industrial Liaison Chair
  • Eric Ollier, CEA-Leti, IRT Nanoelec (FR)

Sponsorship

The DATE'2022 3D Integration: Heterogeneous 3D Architectures and Sensors workshop is technically co-sponsored by IRT Nanoelec.

Registration

For workshop registration, please follow the regular DATE registration web site: online registration platform.

Technical Program

(All times are given in CET time, European Time, UTC+1). 

For time zones, USA changes day time on 13 March, while France changes day time on 27 March. For the workshop on 18 March, there will be 8 hours difference between PST and CET (instead of 9 hours usually).

Workshop Start

8:45 – 9:00           Welcome Note from Organizers

First Keynote

Session Chair : Mustafa Badaroglu, Qualcomm, BE

9:00 – 9:45           “System Design Technology Co-Optimization for 3D Integration”,

                               Seung-Chul (SC) Song, Qualcomm, USA

Session 1 : Chiplet Partitioning and System Level Design

Session Chair : Pascal Vivet, CEA-LIST, France

09:45 – 10:05       “Occamy - A 2.5D Chiplet System for Ultra-Efficient Floating-Point Computing”,

                              Gianna Paulin, ETHZ, Switzerland.

10:05 – 10:25       “Chiplet Based Architecture : an answer for Europe Sovereignty in Computing ?”,

                              Denis Dutoit, CEA, France.

10:25 – 10:45       “Automotive electronic control unit (ECU) for ADAS application based on a Chiplet approach”,

                              Andy Heinig, Fabian Hopsch, Fraunhofer, Germany

10:45 – 11:15       Coffee break

Session 2 : 3D and Image Sensors

Session Chair : Eric Ollier, CEA-Leti, France

 11:15 – 11:35       “Efficient image feature extraction exploiting massive parallelism through 3D-integration”,

                              Ricardo Carmona-Galán, CSIC-University of Seville, Spain.

11:35 – 11:55       “3D Integration for Smart Event Vision Sensors”,

                             Jean-Luc Jaffard, PROPHESEE, France.

11:55 – 12 :15      “3D-stacked CMOS Image Sensors for High Performance Indirect Time-of-Flight”,

                             Cédric Tubert, STMicroelectronics, France

12:15 – 13:30       Lunch

Session 3 : Ultra High Density of 3D, Monolithic 3D

Session Chair : Saibal Mukhopadhyay, GeorgiaTech, USA

13:30 – 13:50       “Thin-film based monolithic 3D systems”,

                              Umesh Chand, Sonu Devi, Hasita Veluri, Aaron Thean, Mohamed Sabry Aly, NTU, Singapore.

13:50 – 14:10       “Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications”,

                             Prachi Shukla, Vasilis F. Pavlidis, Emre Salman, Ayse K. Coskun, Boston Univ., USA; Univ. of Manchester, UK; Stony Brook Univ., USA.

14:10 – 14:30       “A Compute-in-Memory Hardware Accelerator Design with BEOL Transistor based Reconfigurable Interconnect”,

                             Shimeng Yu, GeorgiaTech, USA ; Suman Datta, NotreDam Univ., USA.

14:30 - 14:50       “Nanosystems for Energy-Efficient Computing using Carbon Nanotube FETs and Monolithic 3D Integration”,

                            Tathagata Srimani, Stanford University, USA.

14:50 – 15:15       Coffee break

Second Keynote

Session Chair : Subhasish Mitra, Univ. Stanford, USA.

15:15 – 15:45       “3D stacking opportunities for Augmented Reality hardware systems”,

                               Edith Beigne, META, USA

Session 4 :  3D Design, Methodology and Thermal

Session Chair : Peter Ramm, Fraunhofer EMFT, Germany.

15:45 – 16:05       “EDA Tools and PPA Tradeoff Studies for Micro-bump and Hybrid Bond 3D ICs”,

                               Sung-Kyu Lim, GeorgiaTech, USA.

16:05 – 16:25       “Heterogeneous Packaging Design and Verification Workflows”,

                               Anthony Mastroianni, SIEMENS EDA, USA.

16:25 – 16:45       “Towards a Place and Route Flow for High Density 3D-ICs”,

                               Mauricio Altieri, Olivier Billoint, Sebastien Thuries and Pascal Vivet, CEA, France.

16:45 – 17:05       “Challenges and Opportunities for Thermals in Heterogeneous 3D Packaging”,

                               Rajiv Mongia, INTEL, USA.

Closing

17:05 - 17:30        Closing Remarks

Technical Program

(All times are given in CET time, European Time, UTC+1).

(same information but using DATE web format for information replication within the DATE'2022 Virtual Showcase)