Abstract: Silicon implementations of complex algorithms (for communications and other applications) are burdened by extensive  savety margins to ensure 100% reliable operation. These margins limit voltage scaling at the cost of energy/power consumption and require conservative layout rules such as double-fins or the use of static memories for storage that are costly in area. "Approximate computing" or "computing on unreliable silicon" promotes the idea to compromise reliability and tolerate occasional errors or parameter variations for the benefit of area and power/energy. This idea is especially relevant for applications such as communications or machine learning, where systems are anyway tolerant to noise or apply only stochastic quality metrics such as BER, FER, PSNR, or MSE.
Unfortunately, the silicon industry has so far refused to even remotely consider any idea that involves compromising 100% reliable operation.
The good reason for this strict conservative, but costly (in area and power) approach is that the nature of errors (e.g., due to variations in the manufacturing process) are highly unpredictable and that it is almost impossible to predict the impact of a small error in the silicon on quality of results (e.g., on the error rate in a communication receiver). In fact, reliability issues lead to a huge quality spread between manufactured chips even for the most fault tolerant applications. However, chip manufacturers must provide reliable quality guarantees to their customers. While for example a slightly degraded, but consistent error rate performance or image quality is perfectly acceptable, it is not acceptable if some  circuits provide good quality, while others provide only poor quality.
The key to successfully exploit quality margins for the benefit of area and power is therefore not necessarily to minimize errors, but to ensure that all manufactured chips provide the same quality level, even if they are subject to different more or less random errors.
In this talk, we will explain this issue in detail by analyzing the nature of those errors that approximate computing promotes to tolerate. We argue that the randomness of errors is not only a curse, but can also be a beautiful characteristic that enables reliable quality guarantees. However, this beauty is not always naturally present in the silicon manufacturing process, but it can be restored. We will illustrate this with different examples, including an embedded system with a voltage-over-scaled SRAM and with the first silicon implementation of an LDPC decoder that overcomes the limitations of an unreliable memory.

Bio: Andreas Burg (S'97-M'05) was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree from the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, in 2000, and the Dr. sc. techn. degree from the Integrated Systems Laboratory of ETH Zurich, in 2006.
In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he worked at Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he was a postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. In January 2011, he joined the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory. He was promoted to Associate Professor with Tenure in June 2018.
Mr. Burg has served on the TPC of various conferences on signal processing, communications, and VLSI. He was a TPC co-chair for VLSI-SoC 2012 and the TCP co-chair for ESSCIRC 2016 and SiPS 2017. He was a General Chair of ISLPED 2019 and he served as an Editor for the IEEE Transaction of Circuits and Systems in 2013 and on the Editorial board of the Springer Microelectronics Journal. He is currently an editor of the Springer Journal on Signal Processing Systems, the MDPI Journal on Low Power Electronics and its Applications, the IEEE Transactions on VLSI, and the IEEE Transactions on Signal Processing. He is also a member of the EURASIP SAT SPCN and the IEEE CAS-VSATC.

Abstract: Forward-error-correction codes (FECs) are essential elements in the field of optical communication to deliver an ultra-reliable transmission. In the last decade, communication engineers are unprecedentedly eager to power-efficient FECs due to the scaling down of Moore’s law and the increasing demand of data rate. Typically, the area and power consumption of nowadays high speed FECs are dominated by memories. Embedded DRAM (eDRAM) is a promising approach to deal with this issue due to the fewer transistors. Algorithm and circuit can be co-designed, and refresh module can be removed in such a domain-specific eDRAM. By using non-refresh eDRAM instead of conventional SRAM, significant power reduction and area saving can be achieved in high-speed FECs.
This talk will address the eDRAM-based implementation issues on some mainstream optical FECs, focuses on staircase code and zipper code. The former is a widely adopted standardized FEC and the latter is an upgraded version of staircase code, which was proposed recently.

Abstract: A distributed massive MIMO channel sounder for acquiring CSI datasets is presented. The measured data has several applications in the study of different machine learning algorithms. Each individual single-antenna receiver is completely autonomous, enabling arbitrary grouping into spatially distributed antenna deployments, and offering virtually unlimited scalability in the number of antennas. Some of the deep learning applications presented include absolute and relative user localization like “channel charting”, and CSI inference for UL/DL FDD massive MIMO operation.

Bio: Stephan ten Brink has been a faculty member at the University of Stuttgart, Germany, since July 2013, where he is head of the Institute of Telecommunications. From 1995 to 1997 and 2000 to 2003, Dr. ten Brink was with Bell Laboratories in Holmdel, New Jersey, conducting research on multiple antenna systems. From July 2003 to March 2010, he was with Realtek Semiconductor Corp., Irvine, California, as Director of the wireless ASIC department, developing WLAN and UWB single chip MAC/PHY CMOS solutions. In April 2010 he returned to Bell Laboratories as Department Head of the Wireless Physical Layer Research Department in Stuttgart, Germany. Dr. ten Brink is an IEEE Fellow, and recipient and co-recipient of several awards, including the Vodafone Innovation Award, the IEEE Stephen O. Rice Paper Prize, and the IEEE Communications Society Leonard G. Abraham Prize for contributions to channel coding and signal detection for multiple-antenna systems. He is best known for his work on iterative decoding (EXIT charts), MIMO communications (soft sphere detection, massive MIMO), and deep learning applied to communications.

Abstract: As the great success of artificial intelligence algorithms, machine learning SoC are becoming a significant type of high performance processors recently. However, the limited power budget of edge devices cannot support GPUs and intensive DRAM access. The talk will discuss multiple energy efficient codesign examples to avoid power hungry hardware. First, on-chip incremental learning is performed on an SoC without dedicated backpropagation computing, where algorithm-architecture codesign is involved. Second, low bit-width quantization schemes are applied to computing-in-memory based SoC, where algorithm-circuit codesign is investigated. Moreover, data flow optimization is mapped onto a multi-chiplet-module system, where architecture-package codesign is discussed.

Abstract: Convolutional Neural Networks (CNN) are featured with different bit widths at different layers and have been widely used in mobile and embedded applications. The implementation of a CNN may include multipliers which might consume large overheads and suffer from a high timing error rate due to their large delay. The Pass transistor logic (PTL) based multiplier is a promising solution to such issues. It uses less transistors. It also reduces the gates in the critical path and thus reduces the worst case delay. As a result, the timing error rate is reduced. In this talk, we present PTL based multipliers and the design for test (DFT). An error model is built to analyze the error rate and to help with DFT. According to the simulation results, compared to traditional CMOS based multiplier, the operation ability (measured by Joule per operation, J/OPS) of PTL multipliers could be reduced by over 20%.

Abstract: In this talk, we will introduce an ultra-low-power neural processing SoC chip with computing-in-memory technology. We have designed, fabricated, and tested chips based on nonvolatile floating-gate technology nodes. It simultaneously solves the data processing and communication bottlenecks in NNs. Furthermore, thanks to the nonvolatility of the floating-gate cell, the computing-in-memory macros can be powered down during the idle state, which saves leakage power for an IoT uses, e.g., for voice commands recognition. The chip supports multiple NNs including DNN, TDNN, and RNN for different applications.

Abstract: Computing-in-memory (CIM) is an emerging technique to solve the memory-wall bottleneck. It can reduce data movement between memory and processor, and have significant power reduction in neural network accelerators, especially in edge devices. Communication system is facing the power issue and heat dissipation problem while implementaing the DSP algorithm with ASIC. It will have a great impact if CIM technique can be applied in communication systems to improve the energy efficiency. The talk will discuss computing-in-memory technique for communication systems. Some DSP modules (such as FIR, MIMO and FECs) will be re-organized and mapped onto computing-in-memory units as examples.